Semiconductor device having power MOS transistor including parasitic transistor

ABSTRACT

A semiconductor device has a power MOSFET 12 connected between a semiconductor substrate 21 of N-type as an output terminal 15 and a GND terminal 16 connected to a first semiconductor layer 22 formed on the semiconductor substrate 21 and having a gate connected to a first node for controlling the supply of electric current to a load connected between the GND terminal and the output terminal, a control circuit receiving an input signal and controlling an operation of the power MOSFET in response to the input signal, an input terminal provided in a second semiconductor layer 23 of N-type formed on the first semiconductor layer 22, a parasitic transistor 24 connected between the semiconductor substrate and the second semiconductor layer, and having a base connected to the first semiconductor layer, and switching circuit for keeping the parasitic transistor at a non-conductive state.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and, moreparticularly, to a semiconductor device including a power metal oxidesilicon field effect transistor.

2. Description of the Related Art

A power metal oxide silicon field effect transistor (MOSFET) has beenwidely used recently because it can drive a large load at a high speed.

A circuit diagram illustrating a conventional semiconductor device is inFIG. 6.

As shown in FIG. 6, the conventional semiconductor device is constitutedby an input signal source 9 for generating an input signal, a currentlimiting resistor 10 for limiting electric current flowing through thedevice, a power supply 13, a load 14, a power MOSFET 12 for controllingthe supply of current to the load 14, a constant-voltage diode 25, adiode 26, and a control circuit 17 for controlling the operation of thepower MOSFET 12; provided in the control circuit 17 and connected inparallel between an input terminal 3 and a GND terminal 16 are aresistor 1 and a constant-voltage diode 2, resistors 4 and 5, acomparator 6 for performing comparison of the value of the voltage whichhas undergone the division through the resistors 4, 5, and a P channel(Pch) MOSFET 7 and an N channel (Nch) MOSFET 8 in which the outputs fromthe comparator 6 are applied to the gate terminals thereof, a resistor11 also being included in the control circuit 17, which resistor 11 hasone end thereof connected to the drain terminals of the PchMOSFET 7 andNchMOSFET 8 and the other end thereof connected to the gate terminal ofthe power MOSFET 12; and there is also included a parasitic NPN bipolartransistor 24 having an emitter terminal thereof connected to the inputterminal 3 and a collector terminal thereof connected to an outputterminal 15.

FIG. 7 is a cross-sectional view showing the structure of thesemiconductor device illustrated in FIG. 6.

As shown in FIG. 7, the conventional semiconductor device is comprisedof an N⁺ substrate 21 serving as the output of the power MOSFET 12, a P⁻semiconductor layer 22 joined onto the N⁺ substrate 21, and an N⁻semiconductor layer 23 which is joined onto the P⁻ semiconductor layer22 and which has the control circuit 17.

The operation of the semiconductor device configured as described abovewill now be described.

FIG. 8 illustrates the operation of the semiconductor device shown inFIG. 6 and FIG. 7; (a) shows the voltage of a signal output from theinput signal source 9 and the voltage value at the input terminal 3, (b)illustrates the output voltage of the comparator 6, (c) illustrates thegate voltage of the power MOSFET 12, and (d) illustrates the voltagevalue and the current value at the output terminal 15.

When the voltage output from the input signal source 9 rises and whenthe value of the voltage, which has undergone the division through theresistors 4 and 5, exceeds the constant voltage of the constant-voltagediode 2 (t1) via PchMOSFET 7, the output of the comparator 6 switches toa low level.

This turns the PchMOSFET 7 ON and turns the NchMOSFET 8 OFF.

Thus, electric charge is accumulated at the gate of the power MOSFET 12and the power MOSFET 12 is placed in an ON state, causing electriccurrent to flow into the load 14.

Next, the voltage output from the input signal source 9 lowers and whenthe value of the voltage, which has undergone the division through theresistors 4 and 5, goes down to the constant voltage of theconstant-voltage diode 2 or lower (t2) via Nch MOSFET 8, the output ofthe comparator 6 switches to a high level.

Then the PchMOSFET 7 turns OFF, whereas the NchMOSFET 8 turns ON.

This causes the electric charge, which has been accumulated at the gateof the power MOSFET 12, to be discharged, and the power MOSFET 12 ischanged to an OFF state.

And the reactance component of the load 14 leads to a rise in thevoltage at the output terminal 15, and when the voltage at the outputterminal 15 exceeds the constant voltage value of the constant-voltagediode 25, electric current flows from the NchMOSFET 8 to the GNDterminal 16 or from the drain of the PchMOSFET 7 to the input terminal 3through the constant-voltage diode 25, the diode 26, and the resistor11.

This in turn causes the gate voltage of the power MOSFET 12 to becontinued to be biased; the bias allows electric current to flow intothe power MOSFET 12 due to so-called "dynamic clamping."

In the conventional semiconductor device described above, however, theparasitic NPN transistor 24 is actuated whenever the voltage at theinput terminal 3 drops below the voltage at the GND terminal 16, posinga problem in that electric current flows from the output terminal 15 tothe input terminal 3, damaging the device.

More specifically, as shown in FIG. 7, in the foregoing conventionalexample, the parasitic NPN transistor 24 is designed so that the N⁺substrate 21 serves as the collector, the P⁻ semiconductor layer 22serves as the base, and the N⁻ semiconductor layer 23 serves as theemitter; therefore, with the voltage applied to the output terminal 15,the voltage at the input terminal 3 becomes lower than the voltage atthe GND terminal 16, and when the difference therebetween exceeds thevoltage between the base and the emitter to cause electric current toflow from the GND terminal 16 to the input terminal 3, thus undesirableactuating the parasitic NPN transistor 24.

In particular, when a high voltage (e.g. 70 V) is applied to the outputterminal 15 in such a case as the dynamic clamping, a second breakdownwhich is peculiar to a bipolar transistor results with a consequencegreater chance of damage to the device.

To cope with the difficulty, a device for protecting a semiconductordevice from damage has been disclosed in Japanese Patent ApplicationLaid Open No. Hei 5-58583.

FIG. 9 is a block diagram illustrative of the sketch of thesemiconductor device.

As shown in FIG. 9, the device includes a MOSFET 31 having a highthreshold voltage V_(T) connected between the input terminal 3 and theGND terminal 16; when static electricity is applied to the inputterminal 3 and when the voltage between the input terminal 3 and the GNDterminal 16 exceeds the threshold voltage V_(T) (approximately 20 to 25V in this example), the second breakdown results, thus turning theMOSFET 31 ON.

However, the problem in the semiconductor device shown in FIG. 6 is thedamage to the device caused by the parasitic NPN transistor 24 which isactuated when the voltage at the input terminal 3 is lower than thevoltage at the GND terminal 16; therefore, the publicly known exampleillustrated in FIG. 9 does not make sense.

There is another publicly known example, namely, "Supply TerminalProtection" of "Reverse-Voltage Protection Methods for CMOS Circuits"(IEEE JOURNAL Vol24, February 1989).

FIG. 10 is a block diagram showing the sketch of the semiconductordevice, and FIG. 11 is a cross-sectional view illustrative of thestructure of the device shown in FIG. 10.

As shown in FIG. 10 and FIG. 11, the device has a PchMOSFET 34 connectedbetween V_(DD) 32 and an N substrate 33 to prevent short-circuit currentfrom flowing through a parasitic diode 35 when V_(DD) <V_(SS).

In the semiconductor device shown in FIG. 6, however, since the currentlimiting resistor 10 is inserted, there is no need to provide preventivemeasures against short-circuit current even when the V_(DD) 32 isreplaced by the input and the V_(SS) by GND. Further, mounting the powerMOSFET on the device shown in FIG. 10 and FIG. 11 inevitably makes ahigh voltage-withstand horizontal type power MOSFET which provides anundesirable high ON resistance (e.g. approximately 1.5 times for 70-voltvoltage withstand).

The present invention has been accomplished in view of the problems withthe prior arts described above, and it is an object of the presentinvention to provide a semiconductor device which is capable ofpreventing the damage to the device caused by the undesirable actuationof a parasitic NPN parasitic transistor.

SUMMARY OF THE INVENTION

It is therefore a principal object to provide a power MOSFET having acircuit for preventing a parasitic transistor from actuating.

A semiconductor device according to the present invention, an inputsignal source for generating an input signal, a first power terminalprovided in a first semiconductor layer of a second conductivity typeformed on a semiconductor substrate, a power MOSFET connected betweensaid first power terminal and said semiconductor substrate of a firstconductivity type as an output terminal and having a gate connected to afirst node for controlling the supply of electric current to a loadconnected between said first power terminal and said output terminal, acontrol circuit receiving said input signal for controlling an operationof said power MOSFET in response to said input signal, an input terminalprovided on a second semiconductor layer of said second conductivitytype formed on said first semiconductor layer, a parasitic transistorhaving a first terminal connected to said second semiconductor layer, asecond terminal connected to said semiconductor substrate, and a baseterminal connected to said first semiconductor layer, and a switchingcircuit for keeping said parasitic transistor at non-conductive statewhen a voltage of said input terminal changes.

Therefore, the parasitic transistor is not actuated, making it possibleto prevent damage to the semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the presentinvention will be more apparent from the following description taken inconjunction with the accompanying drawings, in which

FIG. 1 is a circuit diagram showing a first embodiment of asemiconductor device in accordance with the present invention;

FIG. 2 is a cross-sectional view showing the structure of thesemiconductor device shown in FIG. 1;

FIG. 3 is a circuit diagram showing a second embodiment of thesemiconductor device in accordance with the present invention;

FIG. 4 is a diagram for illustrating the operation of the semiconductordevice shown in FIG. 3; (a) is a chart showing the voltage value at aninput terminal, (b) is a chart showing the source voltage of aPchMOSFET, and (c) is a chart showing the voltage value and the currentvalue at an output terminal;

FIG. 5 is a circuit diagram showing a third embodiment of thesemiconductor device in accordance with the present invention;

FIG. 6 is a circuit diagram showing a conventional semiconductor device;

FIG. 7 is a cross-sectional view illustrating the structure of thesemiconductor device shown in FIG. 6;

FIG. 8 a diagram for illustrating the operation of the semiconductordevice shown in FIG. 6 and FIG. 7; (a) is a chart showing the voltage ofa signal issued from an input signal source 9 and the voltage value atan input terminal 3, (b) is a chart showing the output voltage of acomparator 6, (c) is a chart showing the gate voltage of a power MOSFET12, and (d) is a chart showing the voltage value and the current valueat an output terminal 15;

FIG. 9 is a block diagram showing the sketch of the conventionalsemiconductor device;

FIG. 10 is a block diagram showing the sketch of another conventionalsemiconductor device; and

FIG. 11 is a cross-sectional view showing the structure of the deviceshown in FIG. 10.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will now be described withreference to the accompanying drawings.

As shown in FIG. 1, the embodiment is constituted by an input signalsource 9 for generating an input signal, a current limiting resistor 10for limiting electric current flowing through the device, a power supply13, a load 14, a power MOSFET 12 for controlling the supply of electriccurrent to the load 14, a constant-voltage diode 25, a diode 26, acontrol circuit 17 for controlling the operation of the power MOSFET 12,an NchMOSFET 20 which is a first MOSFET and a PchMOSFET 18 which is asecond MOSFET serving as a first switch for controlling the operation ofthe NchMOSFET 20, which are connected in parallel between an inputterminal 3 and a GND terminal 16 of the control circuit 17, and aresistor 19 connected in series to the PchMOSFET 18; provided in thecontrol circuit 17 and connected in parallel between the input terminaland the GND terminal are a resistor 1 and a constant-voltage diode 2,resistors 4 and 5, the comparator 6 which performs the comparison of thevalue of the voltage which has undergone the division through theresistors 4, 5, a PchMOSFET 7 and an NchMOSFET 8 in which the outputsfrom the comparator 6 are applied to the gate terminals thereof; alsoincluded in the control circuit 17 is a resistor 11 having one endthereof connected to the drain terminals of the PchMOSFET 7 and theNchMOSFET 8 and the other end thereof connected to the gate terminal ofthe power MOSFET 12; and there is also a parasitic NPN transistor 24having a base terminal thereof connected to the GND terminal 16, anemitter terminal thereof connected to the input terminal 3, and acollector terminal thereof connected to an output terminal 15. In theNchMOSFET 20, the gate terminal is connected to the GND terminal 16 viaa resistor 19, the source terminal is connected to the GND terminal 16,and the drain terminal is connected to the input terminal 3; and in thePchMOSFET 18, the gate terminal is connected to the input terminal 3,the drain terminal is connected to the gate terminal of the NchMOSFET20, and the source terminal is connected to the gate terminal of thepower MOSFET 12.

In the semiconductor device configured as described above, the resistor1 and the constant-voltage diode 2 together generate a referencevoltage; the reference voltage is compared with the value of voltage,which has been applied through the input terminal 3 and has undergonethe division through the resistors 4 and 5, in the comparator 6.

As shown in FIG. 2, the embodiment is comprised of an N⁺ substrate 21serving as the output of the power MOSFET 12, a P⁻ semiconductor layer22 which is a first semiconductor layer joined onto the N⁺ substrate 21,and an N⁻ semiconductor layer 23 serving as a second semiconductor layerwhich has the control circuit 17; the output terminal 15 is provided onthe N⁺ substrate 21, the input terminal 3 is provided on the N⁻semiconductor layer 23, and the GND terminal 16 is provided on the P⁻semiconductor layer 22, respectively.

The operation of the semiconductor device configured as described abovewill now be described.

When the voltage output from the input signal source 9 rises and whenthe value of the voltage, which has undergone the division through theresistors 4 and 5, exceeds the constant voltage of the constant-voltagediode 2, the output of the comparator 6 switches to a low level.

This turns the PchMOSFET 7 ON and turns the NchMOSFET 8 OFF.

Thus electric charge is accumulated at the gate of the power MOSFET 12and the power MOSFET 12 is placed in an ON state, causing electriccurrent to flow from the power supply 13 to the load 14, the outputterminal 15, and the GND terminal 16.

Next, the voltage output from the input signal source 9 lowers and whenthe value of the voltage, which has undergone the division through theresistors 4 and 5, goes down to the constant voltage of theconstant-voltage diode 2 or lower, the output of the comparator 6switches to a high level.

Then the PchMOSFET 7 turns OFF, whereas the NchMOSFET 8 turns ON.

This causes the electric charge, which has been accumulated at the gateof the power MOSFET 12, to be discharged. At this time, the PchMOSFET 18turns ON, causing a voltage to be applied to the resistor 19, turning ONthe NchMOSFET 20.

This, as illustrated in FIG. 2, causes the base and the emitter of theparasitic NPN transistor 24 to be short-circuited, wherein the parasiticNPN transistor 24 uses as the collector thereof the N⁺ substrate 21serving as the output of the power MOSFET 12, uses as the base thereofthe P⁻ semiconductor layer 22 connected to the GND terminal 16, and usesas the emitter thereof the N⁻ semiconductor layer 23; therefore, evenwhen the voltage at the input signal source 9 is the voltage at the GNDterminal 16 or lower, the voltage difference between the base and theemitter can be made smaller than the operating voltage (approximately0.7 V) between the base and the emitter of the parasitic NPN transistor24, making it possible to prevent the parasitic NPN transistor 24 frombeing actuated.

Next, when the gate voltage of the power MOSFET 12 goes down, thevoltage at the output terminal 15 goes up, and electric current flows tothe input terminal 3 or the PchMOSFET 18, the resistor 19, and the GNDterminal 16 via the constant-voltage diode 25, the diode 26, theresistor 11, and between the drain and the source of the PchMOSFET 7.

The electric current biases the gate of the MOSFET 12, so that theenergy accumulated at the reactance of the load 14 is discharged, andthe PchMOSFET 18 is turned ON and kept ON, that is, the NchMOSFET 20 isturned ON and kept ON, until the voltage at the output terminal 15 goesdown, thus preventing the parasitic NPN transistor 24 from beingactuated while the voltage at the output terminal 15 is high.

Therefore, when the electric charge accumulated in the power MOSFET isdischarged, the first switch is operated to turn ON the first MOSFET soas to cause short circuit across the base and the emitter of theparasitic transistor. Thus, the parasitic transistor is not actuated,making it possible to prevent damage to the semiconductor device.

FIG. 3 is a circuit diagram showing a second embodiment of thesemiconductor device in accordance with the present invention.

As shown in FIG. 3, the embodiment is constituted by an input signalsource 9 for generating an input signal, a power supply 13, a load 14, apower MOSFET 12 for controlling the supply of electric current to theload 14, a control circuit 17 for controlling the operation of the powerMOSFET 12, and a PchMOSFET 27 which is a third MOSFET connected betweenthe input signal source 9 and the control circuit 17; provided in thecontrol circuit 17 and connected in parallel between the source terminalof the PchMOSFET 27 and a GND terminal 16 are a resistor 1 and aconstant-voltage diode 2, resistors 4 and 5, the comparator 6 whichperforms the comparison of the value of the voltage which has undergonethe division through the resistors 4, 5, and a PchMOSFET 7 and aNchMOSFET 8 in which the outputs from the comparator 6 are applied tothe gate terminals thereof; a resistor 11 is also included in thecontrol circuit 17, the resistor 11 having one end thereof connected tothe drain terminals of the PchMOSFET 7 and the NchMOSFET 8 and the otherend thereof connected to the gate terminal of the power MOSFET 12; andthere is also a parasitic NPN transistor 24 having the base terminalthereof connected to the GND terminal 16, the emitter terminal thereofconnected to the source terminal of the PchMOSFET 27, and the collectorterminal thereof connected to an output terminal 15. In the PchMOSFET27, the gate terminal is connected to the GND terminal 16, the sourceterminal is connected to the control circuit 17, and the drain terminalis connected to the input terminal 3.

The operation of the semiconductor device thus configured will now bedescribed.

When the voltage at the input signal source 9 rises and exceeds the sumof the diode voltage (about 0.7 V) across the drain and the source ofthe PchMOSFET 27 and the threshold voltage (about 1 V), the PchMOSFET 27turns ON; and when the voltage at the input signal source 9 rises andreaches a high level, the control circuit 17 causes electric charge tobe accumulated at the gate of the power MOSFET 12, turning the powerMOSFET 12 ON.

Next, when the voltage of the input signal source 9 decreases down tothe voltage at the GND terminal 16 or lower, the electric chargeaccumulated at the gate of the power MOSFET 12 starts to flow into theinput terminal 3 from the PchMOSFET 27, which has the gate thereofbiased, via the resistor 11 and the diode between the drain and thesource of the PchMOSFET 7.

FIG. 4 illustrates the operation of the semiconductor device shown inFIG. 3; (a) shows the voltage value at the input terminal 3, (b) showsthe voltage of the source of the PchMOSFET 27, and (c) shows the voltagevalue and the current value at the output terminal 15.

When the source voltage of the PchMOSFET 27 reaches judgment voltageV_(IHL) for determining the low level and the high level of the controlcircuit 17, the NchMOSFET 8 is placed in the ON state. This causes thesource voltage of the PchMOSFET 27 to become nearly zero volt and thecontrol circuit 17 stops operating.

Thus, the electric charge accumulated at the gate of the power MOSFET 12is discharged in an unstable state wherein the NchMOSFET 8 is OFF, andupon completion of the discharge, the power MOSFET 12 turns OFF.

At this time, the source voltage of the PchMOSFET 27 graduallydecreases, but it does not lower below the voltage at the GND terminal16 because the PchMOSFET 27 turns OFF at the threshold voltage (about 1V). Hence, the parasitic NPN transistor 24 is not actuated.

As described above, in this embodiment, when the voltage at the inputsignal source 9 decreases down to the voltage at the GND terminal 16 orlower, the electric charge accumulated at the gate of the power MOSFET12 is discharged and electric current flows to the PchMOSFET 27 untilthe discharge is completed. Upon completion of the discharge, theelectric current stops; therefore, the parasitic transistor is notactuated.

FIG. 5 is a circuit diagram showing a third embodiment of thesemiconductor device in accordance with the present invention.

As shown in FIG. 5, this embodiment is composed of an input signalsource 9 for generating an input signal, a power supply 13, a load 14, apower MOSFET 12 for controlling the supply of electric currents to theload 14, a control circuit 17 for controlling the operation of the powerMOSFET 12, and an NchMOSFET 30 which is a fourth MOSFET connected to anoutput stage of the control circuit 17, a PchMOSFET 28 which is a fifthMOSFET serving as a second switch for controlling the operation of theNchMOSFET 30, a resistor 29 connected in series with the PchMOSFET 28,and a PchMOSFET 27 connected between the input signal source 9 and thecontrol circuit 17; included in the control circuit 17 and connected inparallel between the source terminal of the PchMOSFET 27 and a GNDterminal 16 are a resistor 1 and a constant-voltage diode 2, resistors4, 5, a comparator 6 which performs the comparison of the value of thevoltage which has undergone the division through the resistors 4, 5, anda PchMOSFET 7 and an NchMOSFET 8 in which the outputs from thecomparator 6 are applied to the gate terminals thereof; also included inthe control circuit 17 is a resistor 11 having one end thereof connectedto the drain terminals of the PchMOSFET 7 and the NchMOSFET 8 and theother end thereof connected to the gate terminal of the power MOSFET 12;and there is also a parasitic NPN transistor 24 having the base terminalthereof connected to the GND terminal 16, the emitter terminal thereofconnected to the source terminal of the PchMOSFET 27, and the collectorterminal thereof connected to an output terminal 15. In the NchMOSFET30, the gate terminal is connected to the GND terminal 16 via a resistor29, the source terminal is connected to the GND terminal 16, and thedrain terminal is connected to the drain terminals of the PchMOSFET 7and the NchMOSFET 8. In the PchMOSFET 28, the gate terminal is connectedto the input terminal 3, the drain terminal is connected to the gateterminal of the NchMOSFET 30, and the source terminal is connected tothe gate terminal of the power MOSFET 12.

The operation of the semiconductor device thus configured will now bedescribed.

When the voltage at the input signal source 9 lowers down to the voltageat the GND terminal 16 or below, the PchMOSFET 28 turns ON, causing theNchMOSFET 30 to turn ON.

And the electric charge accumulated at the gate of the power MOSFET 12is discharged through the resistor 11 and the NchMOSFET 30.

Thus, the control circuit 17 is placed in the OFF state withoutdeveloping an unstable operation, and the voltage between the gate andthe source of the PchMOSFET 27 becomes nearly zero, stopping the flow ofthe electric current to the PchMOSFET 27.

Hence, even when the signal output from the input signal source 9 isgiven by other semiconductor device or the like having a lower drivingcapability, quick turning OFF can be secured.

In the embodiments described above, the description has been given tothe circuit which employs the Nch power MOSFET and has a parasitic NPNtransistor; if the PchMOSFET is used and the parasitic PNP transistor ispresent, then the similar advantage will be obtained by replacing thePchMOSFET 18 by an NchMOSFET, the NchMOSFET 20 by a PchMOSFET, thePchMOSFET 27 by an NchMOSFET, the PchMOSFET 28 by an NchMOSFET, and theNchMOSFET 30 by a PchMOSFET.

Therefore, the emitter voltage of the parasitic transistor does notbecome lower than the base voltage and the parasitic transistor is notactuated. This enables prevention of damage to the semiconductor devicecaused by the parasitic transistor being actuated.

I claim:
 1. A semiconductor device comprising:an input signal source forgenerating an input signal; a first power terminal provided in a firstsemiconductor layer of a second conductivity type formed on asemiconductor substrate; a power MOSFET connected between said firstpower terminal and an output terminal connected to said semiconductorsubstrate of a first conductivity types said power MOSFET having a gateconnected to a first node for controlling a supply of electric currentto a load connected between said first power terminal and said outputterminal; a control circuit receiving said input signal for controllingan operation of said power MOSFET in response to said input signal; aninput terminal provided on a second semiconductor layer of said secondconductivity type formed on said first semiconductor layer; a parasitictransistor having a first terminal connected to said secondsemiconductor layer, a second terminal connected to said semiconductorsubstrate, and a base terminal connected to said first semiconductorlayer; a first transistor of the first conductivity type connectedbetween said input terminal and said first power terminal, said firsttransistor having a gate terminal connected to a second node; and afirst switch connected between said first node and second node forturning on said first transistor when a voltage of said first node ishigher than a voltage of said second node.
 2. The semiconductor deviceaccording to claim 1, whereinsaid first switch has a second MOSFET ofsaid second conductive type connected between said first node and saidsecond node and having a gate connected to said input node, and aresistive element connected between said second node and said firstpower terminal.
 3. A semiconductor device comprising:an input signalsource for generating an input signal; a first power terminal providedin a first semiconductor layer of a second conductivity type formed on asemiconductor substrate; a power MOSFET connected between said firstpower terminal and an output terminal connected to said semiconductorsubstrate of a first conductivity type, said power MOSFET having a gateconnected to a first node for controlling the supply of electric currentto a load connected between said first power terminal and said outputterminal; a control circuit receiving said input signal for controllingan operation of said power MOSFET in response to said input signal; aninput terminal provided on a second semiconductor layer of said secondconductivity type formed on said first semiconductor layer; a parasitictransistor having a first terminal connected to said secondsemiconductor layer, a second terminal connected to said semiconductorsubstrate, and a base terminal connected to said first semiconductorlayer; and a switching circuit connected between said input terminal andsaid control circuit, said switching circuit connecting said inputterminal to said control circuit when a voltage of said input terminalis higher than a predetermined voltage, and said switching circuitdisconnecting said input terminal from said control circuit when avoltage of said input terminal is lower than said predetermined voltage;wherein said switching circuit has a first transistor of said firstconductivity type connected between said input terminal and said controlterminal and having gate connected to said first power terminal.
 4. Asemiconductor device comprising:an input signal source for generating aninput signal; a first power terminal provided in a first semiconductorlayer of a second conductivity type formed on a semiconductor substrate;a power MOSFET connected between said first power terminal and an outputterminal connected to said semiconductor substrate of a firstconductivity types said power MOSFET having a gate connected to a firstnode for controlling a supply of electric current to a load connectedbetween said first power terminal and said output terminal; a controlcircuit receiving said input signal for controlling an operation of saidpower MOSFET in response to said input signal; an input terminalprovided on a second semiconductor layer of said second conductivitytype formed on said first semiconductor layer; a parasitic transistorhaving a first terminal connected to said second semiconductor layer, asecond terminal connected to said semiconductor substrate, and a baseterminal connected to said first semiconductor layer; a first switchingcircuit connected between said input terminal and said control circuitsaid first switching circuit connecting said input terminal to saidcontrol circuit when a voltage of said input terminal is higher than afirst predetermined voltage, and said first switching circuitdisconnecting said input terminal from said control circuit when avoltage of said input terminal is lower than said first predeterminedvoltage; and a second switching circuit connected between said firstnode and said first power terminal for discharging an electric charge ofsaid power MOS transistor when a voltage of said input terminal is lowerthan a second predetermined voltage.
 5. The semiconductor deviceaccording to claim 4, wherein said first switching circuit has a firsttransistor of said first conductivity type connected between said inputterminal and said control terminal and having gate connected to saidfirst power terminal.
 6. The semiconductor device according to claim 4,wherein said second switching circuit has a second transistor of saidsecond conductivity type connected between said first node and saidfirst power terminal and having a gate connected to a third node, athird transistor of said first conductivity type connected between saidfirst node and said third node and having a gate connected to said inputterminal, and a resistive element connected between said third node andsaid first power terminal.